74LS138 – 3 to 8 Line Decoder IC

74LS138 is a member from ‘74xx’family of TTL logic gates. The chip is designed for decoding or de-multiplexing applications and comes with 3 inputs to 8 output setup. The design is also made for the chip to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high performance memory systems these decoders can be used to minimize the effects of system decoding. The three enable pins of chip (in which Two active-low and one active-high) reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented with no external inverters, and a 32-line decoder requires only one inverter.

74LS138 is used in de-multiplexing applications by using enable pin as data input pin. Also the chip inputs are clamped with high-performance Schottky diodes to suppress line-ringing and simplify system design.

74LS138 Pin configuration

74LS138 is a sixteen pin device as shown in pin diagram and we will describe the function of each pin below.

The device is available in different packages for the user to choose from.

Features and Electrical characteristics of 74LS138 Decoder

• Designed specifically for high speed
• Incorporates three enable pins to simplify cascading
• De-multiplexing capability
• Schottky clamped for high performance
• ESD protection
• Balanced propagation delays
• Inputs accept voltages higher than VCC
• Supply voltage: 1.0V to 5.5V
• Typical propagation delay: 21nS
• Low power consumption: 32mW
• Operating temperature: -40ºC to +125ºC